1. Field of the Invention
The present invention relates to a solid state imaging device and a method for reading image signals out of the solid state imaging device.
2. Description of Related Art
Various methods for reading image signals of CMOS image sensors have recently been proposed. Generally, in a CMOS image sensor of a column-parallel output mode, a row of pixels is selected from a pixel array and signals generated by the pixels are read simultaneously in a column direction.
In the CMOS image sensor of the column-parallel output mode, circuits for various reading modes are used, such as a circuit which reads pixel output by sampling it with a switched capacitor, a circuit including amplifiers arranged on a column to column basis and a circuit including AD converters on a column to column basis.
Among them, an example of the conventional CMOS image sensor disclosed by Japanese Unexamined Patent Publication No. 2005-252529 including the amplifiers on a column to column basis is explained with reference to FIG. 11.
FIG. 11 is a block diagram illustrating a major part of the conventional solid state imaging device. Referring to FIG. 11, light from a subject enters a pixel array 101 through a lens system (not shown). The pixel array 101 is a CMOS sensor array and includes a plurality of pixels GS arranged in a matrix. Each of the pixels GS has a MOS transistor and a photodiode.
A vertical scanning circuit 103 selects and scans a row of the pixel array 101 according to an address and a control signal given by a timing generator 102. The conventional vertical scanning circuit 103 successively scans the rows of the array to read signals from the pixels in an effective region in a column-parallel mode. For this operation, the vertical scanning circuit 103 drives vertical scanning lines L1 to Ln. As shown in FIG. 8, each of the pixels GS includes a photodiode PD, a reset transistor Trst connected to a power source signal line 151 and controlled by a reset signal line 153, an amplifying transistor Tg connected to a vertical output signal line 161 and a readout transistor Ts controlled by a readout signal line 155 (first configuration). The pixel GS may further include a transfer gate Tt in addition to the photodiode PD, the reset transistor Trst, the amplifying transistor Tg and the readout transistor Ts (second configuration).
In FIG. 11, each of the vertical scanning lines L corresponds to the pixels GS in each row. If the pixels GS are those of the first configuration, each of the vertical scanning lines L also functions as a signal line for supplying pulses φR and φSV. On the other hand, if the pixels GS are those of the second configuration, each of the single vertical scanning lines L also functions as a signal line for supplying pulses φR, φSV and φTX. In order to read the pixels in the column-parallel mode, signal charges from the pixels GS arranged in the row direction in the pixel array 101 are simultaneously read and supplied to the vertical signal lines VL (VL1, VL2, . . . ).
The image signals from the pixels GS of the selected row are read for a horizontal blanking period in a single horizontal scanning period. That is, during the horizontal blanking period, the image signals from the pixels GS of the row selected by the vertical scanning circuit 103 are output in a parallel manner to the vertical signal lines VL1, VL2, . . . , respectively.
The image signals transferred from the pixel array 101 to the vertical signal lines VL are processed by the column amplifier 105. The column amplifier 105 includes amplifiers AP, limiters LM and switches SW which are arranged to correspond to the vertical signal lines VL (to the pixel columns), respectively.
With the provision of the amplifiers AP, CDS (correlated double sampling) circuits for sampling the image signals are formed.
The image signals are read in a parallel manner from the pixels of the row selected in the horizontal blanking period and then sampled by the column amplifier 105. As a horizontal scanning circuit 106 sequentially selects the switches SW in a horizontal transfer period of a horizontal period, the sampled image signals are transferred to a horizontal signal line HL and then supplied to an output circuit 104.
The horizontal signal line HL may be made of three horizontal signal lines HL1, HL2 and HL3. The amplifiers AP (and the limiters LM) are connected to the three horizontal signal lines LH1, LH2 and LH3 via the switches SW, respectively. The amplifiers AP corresponding to the pixel columns, respectively, sequentially activate the horizontal signal lines HL1, HL2 and HL3 to perform the horizontal transfer of the signals. The signals transferred through the horizontal signal lines HL1, HL2 and HL3 (outputs of the amplifiers AP) are sequentially selected by a multiplexer MPX, thereby supplying a single line signal to the output circuit 104.
The output circuit 104 performs, for example, AGC (auto gain control) processing and clamp processing, to obtain image signals for a single horizontal scanning period as serial signals. The output circuit 104 further performs A/D conversion to obtain image signals as digital data. Digital gain processing and white balance processing are also executed as digital signal processing.
The image signal which is output from the output circuit 104 after the processing is subjected to signal processing for image display in a display unit or to encoding processing such as formatting and compression to be recorded in a recording medium. Or alternatively, the image signal is sent and output.
The timing generator 102 controls the timings to operate the vertical scanning circuit 103, the horizontal scanning circuit 106, the column amplifier 105 and the output circuit 4. The timing generator 102 controls the timings based on a vertical sync signal and a horizontal sync signal.
According to the conventional column amplifier 105 configured as described above, with the provision of the limiters LM, the current values of the amplifiers AP are ideally kept constant at all times irrespective of the magnitude of the image signals (light intensity) and the gains of the amplifiers AP (C1/C2). Therefore, in a theoretical sense, the power supply level and the ground level are always kept constant even in the presence of parasitic resistance. This makes it possible to avoid problems, such as change in black level and transverse band. Japanese Unexamined Patent Publication No. 2005-252529 further discloses that the amplifier gain is increased by adding cascode MOS transistors to source-grounded amplifiers.
As another example of the solid state imaging device including the amplifiers (e.g., single-end amplifiers) arranged on a column to column basis, Japanese Unexamined Patent Publication No. H5-207220 discloses single-end amplifiers including current source MOS transistors and amplifying MOS transistors.